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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-31101-1E
ASSP for Graphics Control
Graphics Display Controller
MB86290A
s DESCRIPTION
The MB86290A is a graphics display controller for drawing and displaying graphics on a car navigation system or amusement unit. The MB86290A can process high-quality, true three-dimensional graphics at high speed using advanced features such as distortion control and hidden surface removal during expression of various levels of transparency and drawing in three-dimensional space. It can also process two-dimensional graphics with a smooth touch, for example, by drawing smooth lines and drawing polygons by connecting arbitrarily specified vertices.
s FEATURES
* Operating frequency: 100 MHz (External clock of 14.32 MHz Max) * Host interface: Enables direct connection to a CPU (Hitachi SH3/4 or NEC V832). * Drawing features: * Drawing at a peak rate of 800 Mpixels per second (at an internal operating frequency of 100 MHz) * 2D drawing functions: Point, line, triangle, polygon, BLT, and pattern drawing * 3D drawing functions: Point, line, and triangle drawing, and hidden surface removal by Z-buffering * Special effects: Anti-aliasing, bold/dashed-line processing, alpha blending, Gouraud shading, texture mapping (bilinear filtering, perspective correct), and tiling (Continued)
s PACKAGE
240-pin, Plastic QFP
(FPT-240P-M03)
MB86290A
(Continued) * Display features : * Maximum display resolution supported: 1024 x 768 pixels * Color display either with a color palette of 8 bits per pixel or directly using 5-bit RGB colors of 16 bits per pixel * Overlaying four layers of screen, of which two lower layers can be divided into the left and right parts * Supporting two 64x64-pixel hardware cursors * Three-channel D/A converter integrated to output analog RGB signals * Capable of superimposing using an external synchronization mode * Memory interface : * Using SDRAM as graphics memory at an operating clock speed of 100 MHz and data bus width of 64 bits. Capable of connecting up to 32 Mbytes (offering a throughput of 800 Mbps). * Power-supply voltage: Two power supplies at 2.5 V0.2 V for internal circuits and 3.3 V0.3 V for I/O parts * Package: Plastic QFP with 240 pins (with a lead pitch of 0.5 mm) * Power consumption: 1 W (at 100 MHz, VDDL = 2.5 V 0.2 V) * Process technology: 0.25 m CMOS
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MB86290A
s PIN ASSIGNMENT
(TOP VIEW)
240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 INT DREQ RDY D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 VDDH VSS VDDL D10 D11 D12 D13 D14 D15 D16 VSS D17 D18 D19 D20 D21 D22 VDDH VSS VDDL D23 D24 D25 D26 D27 D28 D29 D30 D31 VSS MD0 MD1 MD2 MD3 VDDH VSS VDDL MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 180 WE3 179 WE2 178 WE1 177 WE0 176 DTACK/TC 175 DRACK/DMAAK 174 RD 173 CS 172 VDDL 171 VSS 170 BCLKI 169 BS 168 TEST2 167 TEST1 166 TEST0 165 AVS0 164 S 163 CLK 162 AVD0(VCO) 161 RESET 160 VDDL 159 VSS 158 MD63 157 MD62 156 MD61 155 MD60 154 MD59 153 MD58 152 MD57 151 VSS 150 VDDH 149 MD56 148 MD55 147 MD54 146 MD53 145 MD52 144 MD51 143 MD50 142 VSS 141 MD49 140 MD48 139 MD47 138 MD46 137 MD45 136 MD44 135 MD43 134 MD42 133 VDDL 132 VSS 131 VDDH 130 MD41 129 MD40 128 MD39 127 MD38 126 MD37 125 MD36 124 MD35 123 MD34 122 MD33 121 MD32
VSS/AVS : Ground, VDDH : 3.3 V power supply, VDDL : 2.5 V power supply AVD1 - AVD4 : 2.5 V analog power supply, AVD(VCO) : 2.5 V PLL power supply Notes : * Leave pin 211 open without making any connection. * AVD1 - AVD4, AVD(VCO), and /VDDL should be separated on the board.
MD14 MD15 MD16 MD17 VDDH VSS VDDL MD18 MD19 MD20 MD21 MD22 MD23 MD24 VSS MD25 MD26 MD27 MD28 MD29 MD30 MD31 VDDH VSS VDDL MDQM0 MDQM1 MDQM2 MDQM3 MRAS MCAS MWE MA0 MA1 MA2 MA3 MA4 VDDH VSS MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 CKE MCLKO VDDH VSS VDDL MCLKI TEST5 VSS MDQM4 MDQM5 MDQM6 MDQM7
TEST4 MODE1 MODE0 DCLKI VDDL VSS VDDH DCLKO HSYNC VSYNC CSYNC GV EO ACOMPR VREF VRO AVD4 AOUTR AVS4 AVS3 AVD3 AVS2 AOUTG AVD2 ACOMPG AVS1 AOUTB AVD1 ACOMPB TEST3 CKM A24 VSS A23 A22 A21 A20 A19 A18 VDDL VSS A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 VDDL VSS A7 A6 A5 A4 A3 A2
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MB86290A
s PIN DESCRIPTION
D0 to D31 A2 to A24 BCLKI RESET CS RD WE0 to WE3
MD0 to MD63 MA0 to MD13 CKE MRAS MCAS MWE MDQM0 to MDQM7 MCLKO MB86290A Graphics Controller DCLKO DCKLI HQFP240 AOUTR, AOUTG, AOUTB HSYNC VSYNC MCLKI
Graphics memory interface
Host interface
RDY BS DREQ DRACK DTACK INT MODE0, MODE1 TEST0 to TEST5
CLK
CSYNC EO GV VREF ACOMPR, ACOMPG, ACOMPB VRO
Video interface
Clock input
S CKM
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MB86290A
* Host Interface Pins Pin Name Input/output MODE0, MODE1 RESET D0 to D31 A2 to A24 BCLKI BS CS RD WE0 WE1 WE2 WE3 RDY DREQ DRACK/ DMAAK DTACK/TC INT TEST0 to TEST5 Input Input Input/Output Input Input Input Input Input Input Input Input Input Output Tristate Output Input Input Output Input Host CPU mode select Hardware reset Host CPU bus data Host CPU bus address (Connect A24 to MWR in V832 mode.) Host CPU bus clock Bus cycle start signal Chip select signal Read strobe signal D0 to D7 write strobe signal D8 to D15 write strobe signal D16 to D23 write strobe signal D24 to D31 write strobe signal Wait request signal ("0" for wait state with SH3; "1" for wait state with SH4 or V832) DMA request signal (active low with both SH and V832) InputDMA request acknowledge signal (Connect this to DMAAK in V832 mode. Active high with both SH and V832.) DMA transfer strobe signal (Connect this to TC in V832 mode. SH = active high, V832 = active low) Host CPU interrupt signal (SH = active low, V832 = active high) Test signal
Function
Note : The host interface can connect the MB86290A to the SH4 (SH7750) or SH3 (SH7709) manufactured by Hitachi Ltd. or to the V832 manufactured by NEC without any external circuit in between. (Using the SRAM interface allows the MB86290A to use another CPU.) The host CPU is set by the MODE pins as shown below. MODE1 pin L L H H MODE0 pin L H L H CPU Type SH3 SH4 V832 Reserved
Notes : * The host interface transfers data signals at a fixed width of 32 bits. * There are 23 lines for address signals handled in double words (32 bits) and 32 Mbytes of address space. * The external bus can be used at an operating frequency of 100 MHz Max. * The RDY signal at the low level sets the ready state in the SH4 or V832 mode; the signal at the low level sets the wait state in the SH3 mode. Note that the XRDY signal is a tristate output. * The host interface supports DMA transfer using an external DMA controller. 5
MB86290A
* The host interface generates a host processor interrupt signal. * The RESET pin requires low level input of at least 300 s after setting "S" (PLL reset signal) to high level. * Fix the TEST signal at high level. * In the V832 mode, connect the following pins as specified : Pin Name V832 Signal Name A24 DTACK DRACK MWR TC DMAAK
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MB86290A
* Video Interface Pins Pin Name Input/output DCLKO DCLKI AOUTR AOUTG AOUTB HSYNC VSYNC CSYNC EO GV VREF ACOMPR ACOMPG ACOMPB VRO Output Input Display dot clock signal output External synchronous dot clock signal input
Function
Analog output Analog video (R) signal output Analog output Analog video (G) signal output Analog output Analog video (B) signal output Input/output* Input/output* Output Input/output* Output Horizontal sync signal output Horizontal sync signal input in external synchronization mode Vertical sync signal output Vertical sync signal input in external synchronization mode Composite sync signal output Even/odd-number field identification output Even/odd-number field identification input in external synchronization mode Graphics/video select signal
Analog output Reference voltage input pin Analog output R-signal compensation pin Analog output G-signal compensation pin Analog output B-signal compensation pin Analog output Reference current setting pin
* : Input voltage level : 5 V tolerant Notes : * The video interface contains an 8-bit D/A converter to output analog RGB signals. * Using an additional external circuit, the video interface can use CSYNC signals to generate composite video signals. * The video interface can output analog RGB signals synchronized with external video signals. The mode for synchronization with the DCLKI signal can be selected as well as the mode for synchronization with a set dot clock as for normal display. * The HSYNC and VSYNC signals must be pulled up outside the LSI as they enter the input state upon reset. * Terminate the AOUTR, AOUTG, and AOUTB pins with a resistance of 75 . * Input 1.1 V to the VREF pin. Between this pin and analog ground, insert a bypass capacitor (one with a superior high-frequency characteristic such as a laminated ceramic capacitor) . * Connect the ACOMPR, ACOMPG, and ACOMPB pins to the 0.1F ceramic capacitor ahead of the analog power supply. * Connect the VRO pin to the analog ground with a 2.7 k resistor. * The input voltage levels of the HSYNC, VSYNC, and EO signals are 5 V tolerant. Do not input 5 V to these pins with the power supply off. (See s ABSOLUTE MAXIMUM RATINGS.) * For noninterlaced display in external synchronization mode, input "0" to the EO pin, for example, using a pull-down resistor. * The GV signal serves to switch between graphics and video for chroma keying. The pin outputs a low level signal to select video.
7
MB86290A
* Graphics Memory Interface Pins Pin Name Input/output MD0 to MD63 MA0 to MA13 CKE MRAS MCAS MWE MDQM0 to MDQM7 MCLKO MCLKI Input/output Output Output Output Output Output Output Output Input Graphics memory bus data Graphics memory bus data Clock enable Row address strobe Column address strobe Write enable Data mask Graphics memory clock output Graphics memory clock input
Function
Notes : * The graphics memory interface connects the MB86290A to the external memory used for graphical image data. The interface can directly accept 64 Mbit SDRAM (with a 16-bit or 32-bit data bus) without any external circuit. * The data signal can be selected between 64 bits and 32 bits. To use the 32-bit signal, leave the MD32 to MD63 and MDQM4 to MDQM7 pins open. * Connect the MCLKI pin to the MCLKO pin. * Clock Input Pins Pin Name CLK S CKM
Input/output Input Input Input Clock input signal PLL reset signal Clock mode signal
Function
Notes : * The clock input block inputs the clock signal that serves as the basis for the reference clock for the internal operating clock and display dot clock. Usually input 4 Fsc ( = 14.31818 MHz) . The internal PLL generates the internal operating clock signal of 100.22726 MHz and the display reference clock signal of 200.45452 MHz. * The internal operating clock signal to be used can be selected between the clock signal (CLK input multiplied by 7) generated by the internal PLL and the bus clock BCLKI input to the host CPU interface. Select the BCLKI input to use the host CPU bus at 100 MHz. CKM Clock Mode L H Select internal PLL output. Select host CPU bus clock (BCLKI) .
Note : Immediately after turning the power supply on, input a pulse whose low level period is 500 ns or more to the S pin before setting it to high level. After the S signal goes high, input the RESET signal at low level for 300 s or more.
8
MB86290A
s BLOCK DIAGRAM
External Bus of Host CPU
D0 to D31 Host Interface A2 to A24 Pixel Bus
Display Controller
H/V sync Colorkey
DAC Analog RGB
MD0 to MD63 64 Mbit SDRAM External Memory Controller
2D/3D Rendering Engine
MA0 to MA10
9
MB86290A
s FUNCTION BLOCKS
* Host Interface This block allows the MB86290A to be connected to the SH3 or SH4 microprocessor manufactured by Hitachi Ltd. without any external circuit in between. The block provides an interface to transfer display list and texture pattern data directly from main memory to the CREMSON graphics memory or internal register using the external DMA controller. * External Memory Controller This block controls the external synchronous DRAM connected as graphics memory. The 64-bit or 32-bit data bus is selected and the maximum operating frequency is 100 MHz. * Display Controller This block contains a three-channel D/A converter supporting XGA (1024x768 pixels) display and outputs analog RGB signals. The block enables superimposing using the external synchronization mode. It can divide the screen into the left and right parts to display different contents and to scroll them separately. It can also display animations smoothly using double buffering. In addition, it can overlay up to four screens, where the image color blending function can be used to display maps through the console screen as a transparency. * 2D/3D Rendering Engine This block draws images in two or three dimensions. * 2D drawing The block provides the anti-aliasing and alpha blending functions to display high-quality images even on a lowresolution LCD. * 3D drawing The block provides true 3D drawing functions such as perspective texture mapping and Gouraud shading.
10
MB86290A
s ABSOLUTE MAXIMUM RATINGS
Parameter Power-supply voltage Input voltage Output current Power pin current Ambient operating temperature Ambient storage temperature Symbol VDDL*1 VDDH VI VIV*2 IO IPOW TA Tstg - 0.5 - 13 0 - 40*3 - 55 Rating Min - 0.5 - 0.5 Max + 3.0 + 4.0 VDDH + 0.5 (< 4.0) VDDH + 4.0 (< 6.0) + 13 60 70 + 85*3 + 125 Unit V V V mA mA C C
*1 : The analog and PLL power supplies are included. *2 : The HSYNC, VSYNC, and EO signals are input. *3 : Model supporting a wider range of temperatures WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
11
MB86290A
s RECOMMENDED OPERATING CONDITIONS
Parameter Symbol VDDL*1 Power-supply voltage VDDL*
2
Value Min 2.3 2.6*6 3.0 3.5*6 2.0 2.0 - 0.3 - 0.3 1.05 - 40 Typ 2.5 3.3 1.10 2.7 75 0.1 Max 2.7
Unit
V 3.6 VDDH + 0.3 5.5 + 0.8 + 0.8 1.15 + 85 + 70*6 V V V k F C
VDDH Input voltage (High level) Input voltage (Low level) VREF pin input voltage VRO pin external resistor AOUT pin external resistor*
4
VIH VIHV* VIL VILV*3 VREF RVRO RAOUT CACOMP TA
3
ACOMP pin external capacitor*5 Ambient operating temperature
*1 : The analog and PLL power supplies are included. *2 : The HSYNC, VSYNC, and EO signals are input. *3 : AOUTR, AOUTG, and AOUTB pins *4 : AOUTR, AOUTG, AOUTB pins *5 : ACOMPR, ACOMPG, ACOMPB pins *6 : Using BCLKI at 90 MHz or more Notes : * The VDDL and VDDH power supplies can be turned on or off in either order. Note, however, that the VDDH voltage must not be applied alone continuously for several seconds. * Do not input the HSYNC, VSYNC or signal with the power-supply voltage not applied. (See "Input voltage" in "s ABSOLUTE MAXIMUM RATINGS".) * After turning the power on, input a pulse remaining at low level for at least 500 ns to the S pin. Then, set the S pin to high level and input the RESET signal held at low level for at least 300 s. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
12
MB86290A
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter Output voltage (High level) *1 Output voltage (Low level) *2 Output current (High level) (VDDL = 2.5 V 0.2 V, VDDH = 3.3 V 0.3, VSS = 0.0 V, TA = 0 C to +70 C) Value Symbol Unit Min Typ Max VOH VOL IOH1* IOH2*
3 4
VDDH - 0.2 0.0 - 2.0 - 4.0 - 8.0 2.0 4.0 8.0 9.90 0 - 0.1
10.42 2
VDDH 0.2 10.94 20 + 1.1 5 16
V V mA
IOH3*5 IOL1*3 Output current (Low level) Full scale Zero scale IOL2* IOL3* AOUT voltage*6 AOUT voltage*
7 4 5
mA mA A V A pF
IAOUT VAOUT IL C
Input leakage current Pin capacitance
*1 : Value when -100 A current flows into output pins. *2 : Value when 100 A current flows into output pins. *3 : Output characteristics of the MD0 to MD63, MDQM0 to MDQM7 pins *4 : Output characteristics of the signals (excluding analog signals) other than those in *3 and *5 *5 : MCLKO pin output characteristics *6 : AOUTR, AOUTG, and AOUTB pin output current. Conditions VREF = 1.10 V, RVRO = 2.7 k (The full-scale output current calculation expression is (VREF / RVRO) x 25.575 ) *7 : AOUTR, AOUTG and AOUTB pins
13
MB86290A
2. AC Characteristics
* Input measurement conditions
tr VIH 80% 80% (VIH + VIL) / 2 20% VIL 20% tf
(VIH = 2.0 V, VIL = 0.8 V)
Input
* tr, tf 5 ns * Input measurement standard : (VIH + VIL) / 2
* Output measurement conditions
VIH (VIH + VIL) / 2 VIL
Input
tpHL, tpZL VOH
tpLH, tpZH
Output 1
VOL
VDD/2
VDD/2
tpLZ
Output 2
0.5 V VOL
tpHZ VOH
Output 3
0.5 V
* Output measurement standard : tpLZ : VOL + 0.5 V tpHZ : VOH - 0.5 V Else : VDD/2 14
MB86290A
(1) Host Interface * Clock Parameter BCLKI frequency BCLKI H period BCLKI L period * Host interface signals (Recommended operating conditions A, External load of 20 pF) Parameter Address setup time Address hold time BS setup time BS hold time CS setup time CS hold time RD setup time RD hold time WE setup time WE hold time Write data setup time Write data hold time DTACK setup time DTACK hold time DRACK setup time DRACK hold time Read data delay time (to RD) Read data delay time RDY delay time (to CS) SH Symbol tADS tADH tBSS tBSH tCSS tCSH tRDS tRDH tWES tWEH tWDS tWDH tDAKS tDAKH tDRKS tDRKH tRDDZ tRDD tRDYDZ Condition *1 Value Min 3.0 1.0 3.5 3.0*3 0.0 3.5 3.0*3 0.0 3.0 1.0 3.0 1.0 5.0 4.0*3 1.0 3.0 1.0 3.0 1.0 4.0 4.0 3.0 Max 8.5 7.5*3 9.5 6.0* 9.0 7.5*3
3
Symbol fBCLKI tHBCLKI tLBCLKI
Condition
Value Min 3.5 3.5 Max 100
Unit MHz ns ns
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(Continued)
15
MB86290A
(Continued)
Parameter RDY delay time (to CS) V832 RDY delay time DREQ delay time MODE hold time Symbol tRDYDZ tRDYD tDRQD tMODH Condition *2 Value Min 3.0 3.5 3.5 Max 13.0 10.5*3 8.5 7.0* 7.5 6.5*3 20.0
3
Unit ns ns ns ns ns ns ns
*1 : Read data is output one cycle before the CPU samples it. *2 : Hold time for reset cancellation *3 : Using BCLKI at 90 MHz or more Note: The INT signal is output in synchronization with the internal operating clock. As a host interface signal, it is an asynchronous signal.
16
MB86290A
* Clock
1/fBCLKI tHBCLKI tLBCLKI
BCLKI
* Input setup and hold times
BCLKI
A2~A24, BS, CS, RD, WE, D0~D31, DTACK, DRACK
tADS, tBSS, tCSS, tRDS, tWES, tWDS, tDAKS, tDRKS tADH, tBSH, tCSH, tRDH, tWEH, tWDH, tDAKH, tDRKH
* DREQ output delay time
BCLKI
DREQ (output)
tDRQD
17
MB86290A
* RDY delay value (with respect to CS)
BCLKI
CS
High-Z RDY (output)
tRDYDZ tRDYDZ
High-Z
* RDY/D output delay values
BCLKI
RD
tRDDZ tRDD
D0~D31 (output)
Output data
High-Z
RDY
tRDYD tRDYD
* MODE signal hold time
RESET
MODE0, MODE1
tMODH
18
MB86290A
(2) Video Interface * Clock Parameter CLK frequency CLK H period CLK L period DCLKI frequency DCLKI H period DCLKI L period DCLKO frequency * Input signals Parameter HSYNC input pulse width HSYNC input setup time HSYNC input hold time VSYNC input pulse width EO input setup time EO input hold time Symbol tWHSYNC0 tWHSYNC1 tSHSYNC tHHSYNC tWHSYNC1 tSEO tHEO Condition *1 *2 *2 *2 *3 *3 Value Min 3 3 10 10 1 10 10 Typ Max Unit clock clock ns ns HSYNC 1 cycle ns ns Symbol fCLK tHCLK tLCLK fDCLKI tHDCLKI tLDCLKI fDCLKO Condition Value Min 25 25 5 5 Typ 14.32 Max 67 67 Unit MHz ns ns MHz ns ns MHz
*1 : Applied only in PLL synchronization mode (CKS = 0) . The reference clock is the internal PLL's output with Cycle = 1/ (14 fCLK) . *2 : Applied only in DCLKI synchronization mode (CKS = 1) . The reference clock is DCLKI. *3 : Based on the edge with VSYNC negated. * Output signals Parameter EO output delay time HSYNC output delay time VSYNC output delay time CSYNC output delay time GV output delay time Symbol tDEO tDHSYNC tDVSYNC tDCSYNC tDGV Condition * Value Min Typ Max 10 10 10 10 10 Unit ns ns ns ns ns
* : The EO output varies at the same time as VSYNC is asserted.
19
MB86290A
* Clock
1/fCCLKI tHCCLKI tLCCLKI
CCLKI
* HSYNC signal setup and hold
1/fDCLKI tHDCLKI tLDCLKI
DCLKI
HSYNC (input)
tSHSYNC tHHSYNC
* EO signal setup and hold
VSYNC
EO (input)
tSEO tHEO
* Output signal delay
DCLKO
EO (output) HSYNC (output) VSYNC (output) CSYNC GV
tDEO, tDHSYNC, tDVSYNC, tDCSYNC, tDGV
20
MB86290A
(3) Graphics Memory Interface * Clock Parameter MCLKO frequency MCLKO H period MCLKO L period MCLKI frequency MCLKI H period MCLKI L period MCLKI delay to MCLKO * I/O Symbol fMCLKO tHMCLKO tLMCLKO fMCLKI tHMCLKI tLMCLKI tOID Condition Value Min 1 1 1 1 1 Typ Max 100 100 4 Unit MHz ns ns MHz ns ns ns
signals
Parameter Symbol tMADS tMADH tMDQMDS tMDQMDH tMDODS tMDODH tMDIDS tMDIDH Condition *1 *1 *1 *1 *1 *1 *2 *2 Value Min 3.5 1 3.5 1 3.5 1 3 1 Typ Max Unit ns ns ns ns ns ns ns ns
MA, MRAS, MCAS, MWE, CKE Setup time MA, MRAS, MCAS, MWE, CKE Hold time MDQM data setup time MDQM data hold time MD output data setup time MD output data hold time MD input data setup time MD input data hold time
*1 : Setup/hold time with respect to MCLKO. *2 : Setup/hold time with respect to MCLKI.
21
MB86290A
* Clock
1/fMCLKO, 1/fMCLKI tHMCLKO, tHMCLKI tLMCLKO, tLMCLKI
MCLKO, MCLKI
* Input signal setup and hold times
MCLKO
MD0~MD63
Input data
tMDIDS
tMDIDH
* MCLKI signal delay
MCLKO
MCLKI
tOID
* Output signal delay
MCLKO
MA, MRAS, MCAS, MWE, CKE, MD0~MD63, MDQM0~MDQM7
tMADS, tMDODS, tMDQMDS tMADH, tMDODH, tMDQMDH
22
MB86290A
(4) PLL Standards Parameter Input frequency (Typical) Output frequency Duty ratio Jitter Value Min 93.1 - 150 Typ 14.31818 Max 200.45452 101.3 + 180 Unit MHz MHz % ps Multiplied by 14 PLL output clock H/L pulse width ratio Cycle difference between two consecutive cycles Description
23
MB86290A
s ORDERING INFORMATION
Part Number MB86290APFVS Package 240-pin plastic QFP (FPT-240P-M03) Remarks
24
MB86290A
s PACKAGE DIMENSION
240-pin plastic QFP (FPT-240P-M03)
34.600.20(1.362.008)SQ 32.000.10(1.260.004)SQ
180 121
*Pins width and pins thickness include plating thickness.
3.730.30 (Mounting height) (.147.012)
+0.10 +.004
0.40 -0.15
181 120
.016 -.006
(Stand off)
240
61
Details of "A" part
LEAD No.
1
60
0.50(.020)
0.220.05 (.009.002)
0.08(.003)
M
0.1450.055 (.006.002) 0~8 0.25(.010) 0.45MIN~0.75MAX (.018MIN~.030MAX)
"A"
0.08(.003)
C
2000 FUJITSU LIMITED F240011S-2c-2
Dimensions in mm (inches)
25
MB86290A
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0203 (c) FUJITSU LIMITED Printed in Japan

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